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AD845SQ データシート(PDF) 7 Page - Analog Devices |
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AD845SQ データシート(HTML) 7 Page - Analog Devices |
7 / 8 page AD845 REV. D –7– MEASURING AD845 SETTLING TIME The Figure 24 shows the AD845 settling time performance. This measurement was accomplished by driving the amplifier in the unity-gain inverting mode with a fast pulse generator. The input summing junction was measured using false nulling techniques. Settling time is defined as: The interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. Components of settling time include: 1. Propagation time through the amplifier 2. Slewing time to approach the final output value 3. Recovery time from overload associated with the slewing 4. Linear settling to within a specified error band. These individual components can easily be seen in Figure 24. Settling time is extremely important in high speed applications where the current output of a DAC must be converted to a voltage. When driving a 500 Ω load in parallel with a 100 pF capacitor, the AD845 settles to 0.1% in 250 ns and to 0.01% in 310 ns. Figure 24. Settling Characteristics 0 V to 10 V Step Upper Trace: Output of AD845 Under Test (5 V/Div) Lower Trace: Error Voltage (1 mV/Div) Figure 25. Settling Time Test Circuit A HIGH SPEED INSTRUMENTATION AMP The three op amp instrumentation amplifier circuit shown in Figure 26 can provide a range of gains from unity up to 1000 and higher. The instrumentation amplifier configuration fea- tures high common-mode rejection, balanced differential inputs and stable, accurately defined gain. Low input bias currents and fast settling are achieved with the FET input AD845. Most monolithic instrumentation amplifiers do not have the high frequency performance of the circuit in Figure 26. The cir- cuit bandwidth is 10.9 MHz at a gain of 1 and 8.8 MHz at a gain of 10; settling time for the entire circuit is 900 ns to 0.01% for a 10 V step (Gain = 10). The capacitors employed in this circuit greatly improve the amplifier’s settling time and phase margin. Figure 26. High Performance, High Speed Instrumenta- tion Amplifier Table I. Performance Summary for the Three Op Amp Instrumentation Amplifier Circuit 3 Op-Amp In-Amp Small Signal Settling Time Gain RG Bandwidth to 0.01% 1 Open 10.9 MHz 500 ns 2 2k 8.8 MHz 500 ns 10 226 Ω 2.6 MHz 900 ns 100 20 Ω 290 kHz 7.5 µs Note: Resistors around the amplifiers’ input pins need to be small enough in value so that the RC time constant they form, with stray circuit capacitance, does not reduce circuit bandwidth. Figure 27. The Pulse Response of the Three Op Amp Instrumentation Amplifier. Gain = 1, Horizontal Scale: 0.5 ms/Div; Vertical Scale: 5 V/Div |
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同様の説明 - AD845SQ |
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