AD8631/AD8632

–10–

REV. 0

DRIVING CAPACITIVE LOADS

Capacitive Load vs. Gain

Most amplifiers have difficulty driving capacitance due to degra-

dation of phase margin caused by additional phase lag from the

capacitive load. Higher capacitance at the output can increase the

amount of overshoot and ringing in the amplifier’s step response

and could even affect the stability of the device. The value of

capacitive load that an amplifier can drive before oscillation varies

with gain, supply voltage, input signal, temperature, among oth-

ers. Unity gain is the most challenging configuration for driving

capacitive load. However, the AD8631 offers reasonably good

capacitive driving ability. Figure 22 shows the AD8631’s ability to

drive capacitive loads at different gains before instability occurs.

GAIN – V/V

1M

10

10

2

46

8

10k

1k

100

9

35

7

1

UNSTABLE

STABLE

100k

Figure 22. Capacitive Load vs. Gain

In-the-Loop Compensation Technique for Driving

Capacitive Loads

When driving capacitance in low gain configuration, the in-the-loop

compensation technique is recommended to avoid oscillation as is

illustrated in Figure 23.

1

[

[

AD8631

Figure 23. In-the-Loop Compensation Technique for

Driving Capacitive Loads

Snubber Network Compensation for Driving Capacitive Loads

As load capacitance increases, the overshoot and settling time

will increase and the unity gain bandwidth of the device will

decrease. Figure 24 shows an example of the AD8631 in a non-

inverting configuration driving a 10 k

Ω resistor and a 600 pF

capacitor placed in parallel, with a square wave input set to a

frequency of 90 kHz and unity gain.

TIME – 2 s/DIV

90kHz INPUT SIGNAL

C = 600pF

Figure 24. Driving Capacitive Loads without Compensation

By connecting a series R–C from the output of the device to

ground, known as the “snubber” network, this ringing and over-

shoot can be significantly reduced. Figure 25 shows the network

setup, and Figure 26 shows the improvement of the output

response with the “snubber” network added.

AD8631

5V

Figure 25. Snubber Network Compensation for Capacitive

Loads

TIME – 2 s/DIV

90kHz INPUT SIGNAL

C = 600pF

Figure 26. Photo of a Square Wave with the Snubber

Network Compensation

and provides compensation for the added phase lag. The actual

values of the network resistor and capacitor have to be empirically

determined. Table II shows some values of snubber network for

large capacitance load.