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AD9100AD データシート(PDF) 1 Page - Analog Devices |
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AD9100AD データシート(HTML) 1 Page - Analog Devices |
1 / 12 page FUNCTIONAL BLOCK DIAGRAM A1 VIN CLK CLK A2 SWITCH 50 AD9100 2.3V CLAMP CHOLD 22pF VOUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Ultrahigh Speed Monolithic Track-and-Hold AD9100* FEATURES Excellent Hold Mode Distortion into 250 –88 dB @ 30 MSPS (2.3 MHz VIN) –83 dB @ 30 MSPS (12.1 MHz VIN) –74 dB @ 30 MSPS (19.7 MHz VIN) 16 ns Acquisition Time to 0.01% <1 ps Aperture Jitter 250 MHz Tracking Bandwidth 83 dB Feedthrough Rejection @ 20 MHz 3.3 nV/ √Hz Spectral Noise Density MlL-STD-Compliant Versions Available APPLICATIONS A/D Conversion Direct IF Sampling Imaging/FLIR Systems Peak Detectors Radar/EW/ECM Spectrum Analysis CCD ATE GENERAL DESCRIPTION The AD9100 is a monolithic track-and-hold amplifier which sets a new standard for high speed and high dynamic range applications. It is fabricated in a mature high speed complemen- tary bipolar process. In addition to innovative design topologies, a custom package is utilized to minimize parasitics and optimize dynamic performance. Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and 16 ns to 0.01%. The AD9100 boasts superlative hold-mode frequency domain performance; when sampling at 30 MSPS hold mode distortion is less than 83 dBfs for analog frequencies up to 12 MHz; and –74 dBfs at 20 MHz. The AD9100 can also drive capacitive loads up to 100 pF with little degradation in acquisition time; it is therefore well suited to drive 8- and 10-bit flash converters at clock speeds to 50 MSPS. With a spectral noise density of 3.3 nV/ √Hz and feedthrough rejection of 83 dB at 20 MHz, the AD9100 is well suited to enhance the dynamic range of many 8- to 16-bit systems. The AD9100 is “user friendly” and easy to apply: (1) it requires +5 V/–5.2 V power supplies; (2) the hold capacitor and switch power supply decoupling capacitors are built into the DIP pack- age; (3) the encode clock is differential ECL to minimize clock jitter; (4) the input resistance is typically 800 k Ω; (5) the analog input is internally clamped to prevent damage from voltage transients. The AD9100 is available in a 20-lead side-brazed “skinny DIP” package. Commercial, industrial, and military temperature grade parts are available. Consult the factory for information about the availability of 883-qualified devices. PRODUCT HIGHLIGHTS 1. Hold Mode Distortion is guaranteed. 2. Monolithic construction. 3. Analog input is internally clamped to protect against over- voltage transients and ensure fast recovery. 4. Output is short circuit protected. 5. Drives capacitive loads to 100 pF. 6. Differential ECL clock inputs. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 *Patent pending. |
同様の部品番号 - AD9100AD |
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同様の説明 - AD9100AD |
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