REV. 0

AD9288

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APPLICATION NOTES

THEORY OF OPERATION

The AD9288 ADC architecture is a bit-per-stage pipeline-type

converter utilizing switch capacitor techniques. These stages

determine the 5 MSBs and drive a 3-bit flash. Each stage pro-

vides sufficient overlap and error correction allowing optimiza-

tion of comparator accuracy. The input buffers are differential

and both sets of inputs are internally biased. This allows the

most flexible use of ac or dc and differential or single-ended

input modes. The output staging block aligns the data, carries

out the error correction and feeds the data to output buffers.

The set of output buffers are powered from a separate supply,

allowing adjustment of the output voltage swing. There is no

discernible difference in performance between the two channels.

USING THE AD9288

Good high speed design practices must be followed when using

the AD9288. To obtain maximum benefit, decoupling capacitors

should be physically as close to the chip as possible, minimizing

trace and via inductance between chip pins and capacitor (0603

surface mount caps are used on the AD9288/PCB evaluation

board). It is recommended to place a 0.1

µF capacitor at each

power-ground pin pair for high frequency decoupling, and in-

clude one 10

µF capacitor for local low frequency decoupling.

The VREF IN pin should also be decoupled by a 0.1

µF capaci-

tor. It is also recommended to use a split power plane and

contiguous ground plane (see evaluation board section). Data

output traces should be short (<1 inch), minimizing on-chip

noise at switching.

ENCODE Input

Any high speed A/D converter is extremely sensitive to the qual-

ity of the sampling clock provided by the user. A track/hold

circuit is essentially a mixer. Any noise, distortion or timing

jitter on the clock will be combined with the desired signal at

the A/D output. For that reason, considerable care has been

taken in the design of the ENCODE input of the AD9288, and

the user is advised to give commensurate thought to the clock

source. The ENCODE input is fully TTL/CMOS compatible.

Digital Outputs

The digital outputs are TTL/CMOS compatible for lower

power consumption. During standby, the output buffers transi-

tion to a high impedance state. A data format selection option

supports either twos complement (set high) or offset binary

output (set low) formats.

Analog Input

The analog input to the AD9288 is a differential buffer. For

match. Special care was taken in the design of the analog input

stage of the AD9288 to prevent damage and corruption of

data when the input is overdriven. The nominal input range is

× 0.3.

Voltage Reference

A stable and accurate 1.25 V voltage reference is built into the

reference voltage applied to the AD9288. No appreciable degra-

dation in performance occurs when the reference is adjusted

±5%. The full-scale range of the ADC tracks reference voltage,

which changes linearly.

Timing

The AD9288 provides latched data outputs, with four pipeline

after the rising edge of the encode command (see Figures 1, 2

and 3). The length of the output data lines and loads placed on

them should be minimized to reduce transients within the

AD9288. These transients can detract from the converter’s

dynamic performance.

The minimum guaranteed conversion rate of the AD9288 is

1 MSPS. At clock rates below 1 MSPS, dynamic performance

will degrade. Typical power-up recovery time after standby

mode is 15 clock cycles.

User Select Options

Two pins are available for a combination of operational modes.

These options allow the user to place both channels in standby,

excluding the reference, or just the B channel. Both modes place

the output buffers and clock inputs in high impedance states.

The other option allows the user to skew the B channel output

data by 1/2 a clock cycle. In other words, if two clocks are fed to

the AD9288 and are 180

° out of phase, enabling the data align

will allow Channel B output data to be available at the rising

edge of Clock A. If the same encode clock is provided to both

channels and the data align pin is enabled, then output data

from Channel B will be 180

° out of phase with respect to Chan-

nel A. If the same encode clock is provided to both channels

and the data align pin is disabled, then both outputs are deliv-

ered on the same rising edge of the clock.

EVALUATION BOARD

The AD9288 evaluation board offers an easy way to test the

AD9288. It provides a means to drive the analog inputs single-

endedly or differentially. The two encode clocks are easily

accessible at on-board SMB connectors J2, J7. These clocks are

buffered on the board to provide the clocks for an on-board

DAC and latches. The digital outputs and output clocks are

available at a standard 37-pin connector, P2. The board has

several different modes of operation, and is shipped in the fol-

lowing configuration:

• Single-Ended Analog Input

• Normal Operation Timing Mode

• Internal Voltage Reference

Power Connector

Power is supplied to the board via a detachable 6-pin power

strip, P1.

VREFA –

Optional External Reference Input

(1.25 V/1

µA)

VREFB –

Optional External Reference Input

(1.25 V/1

µA)

VDL

–

Supply for Support Logic and DAC (3 V/215 mA)

VDD

–

Supply for ADC Outputs

(3 V/15 mA)

VD

–

Supply for ADC Analog

(3 V/30 mA)

Analog Inputs

The evaluation board accepts a 1 V analog input signal centered

at ground at each analog input. These can be single-ended sig-

nals using SMB connectors J5 (channel A) and J1 (Channel B).

In this mode use jumpers E4–E5 and E6–E7. (E1–E2 and E9–

E10 jumpers should be lifted.)

Differential analog inputs use SMB connectors J4 and J6. Input

is 1 V centered at ground. The single-ended input is converted