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ADE7759ARS データシート(PDF) 5 Page - Analog Devices |
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ADE7759ARS データシート(HTML) 5 Page - Analog Devices |
5 / 32 page REV. 0 ADE7759 –5– TIMING CHARACTERISTICS 1, 2 Parameter A, B Versions Unit Test Conditions/Comments Write Timing t1 20 ns (min) CS Falling Edge to First SCLK Falling Edge t2 150 ns (min) SCLK Logic High Pulsewidth t3 150 ns (min) SCLK Logic Low Pulsewidth t4 10 ns (min) Valid Data Setup Time Before Falling Edge of SCLK t5 5 ns (min) Data Hold Time After SCLK Falling Edge t6 6.4 µs (min) Minimum Time between the End of Data Byte Transfers t7 4 µs (min) Minimum Time between Byte Transfers During a Serial Write t8 100 ns (min) CS Hold Time After SCLK Falling Edge Read Timing t9 4 µs (min) Minimum Time between Read Command (i.e., a Write to Communications Register) and Data Read t10 4 µs (min) Minimum Time between Data Byte Transfers During a Multibyte Read t11 3 30 ns (min) Data Access Time After SCLK Rising Edge following a Write to the Communi- cations Register t12 4 100 ns (max) Bus Relinquish Time After Falling Edge of SCLK 10 ns (min) t13 4 100 ns (max) Bus Relinquish Time After Rising Edge of CS 10 ns (min) NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3 and Serial Interface section of this data sheet. 3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. (AVDD = DVDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40 C to +85 C unless otherwise noted.) t7 t5 t4 CS SCLK DIN A4 A3 A2 A1 A0 DB7 MOST SIGNIFICANT BYTE 1 DB0 DB7 DB0 LEAST SIGNIFICANT BYTE 00 COMMAND BYTE t1 t2 t3 t6 t7 t8 Figure 2. Serial Write Timing CS SCLK DIN A4 A3 A2 A1 A0 00 0 t1 t10 DOUT DB7 MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE COMMAND BYTE DB0 DB7 DB0 t13 t12 t9 t11 t11 Figure 3. Serial Read Timing TO OUTPUT PIN 2.1V 1.6mA IOH IOL 200 A CL 50pF Figure 1. Load Circuit for Timing Specifications |
同様の部品番号 - ADE7759ARS |
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同様の説明 - ADE7759ARS |
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