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ADMC300 データシート(PDF) 11 Page - Analog Devices

部品番号 ADMC300
部品情報  High Performance DSP-Based Motor Controller
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ADMC300 データシート(HTML) 11 Page - Analog Devices

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ADMC300
–11–
REV. B
Table IV. ROM Utilities
Utility
Address
Function
PER_RST
0x07E4
Peripheral Reset.
UMASK
0x0E21
Limits Unsigned Value to Given
Range.
PUT_VECTOR
0x0E28
Facilitates User Setup of Vector
Table.
SMASK
0x0E35
Limits Signed Value to Given
Range.
ADMC_COS
0x0E55
Cosine Function.
ADMC_SIN
0x0E5C
Sine Function.
ARCTAN
0x0E72
Arctangent Function.
RECIPROCAL
0x0E94
Reciprocal (1/x) Function.
SQRT
0x0EAA
Square Root Function.
LN
0x0EE4
Natural Logarithm Function.
LOG
0x0EE7
Logarithm (Base 10) Function.
FLTONE
0x0F03
Fixed Point to Floating Point
Conversion.
FIXONE
0x0F08
Floating Point to Fixed Point
Conversion.
FPA
0x0F0C
Floating Point Addition.
FPS
0x0F1B
Floating Point Subtraction.
FPM
0x0F2B
Floating Point Multiplication.
FPD
0x0F34
Floating Point Division.
FPMACC
0x0F55
Floating Point Multiply and
Accumulate.
PARK
0x0F77
Forward and Reverse Park
Transformation (Vector
Rotation).
REV_CLARK
0x0F8B
Reverse Clark Transformation.
FOR_CLARK
0x0FA1
Forward Clark Transformation.
SDIVQINT
0x0FAB
Unsigned Single Precision
Division (Integer).
SDIVQ
0x0FB4
Unsigned Single Precision
Division (Fractional).
EXIT
0x0FC6
Exit to Debugger after Running
User Program.
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC300
with an external crystal and serial E
2PROM for boot loading of
program and data memory RAM.
ADMC300
XTAL
CLKIN
DR1A
SCLK1
RFS1/
SROM
DATA
CLK
RESET
12.5 MHz
CLKOUT
RESET
SERIAL
E2PROM
20pF
20pF
Figure 4. Basic System Configuration
Clock Signals
The ADMC300 can be clocked by either a crystal or a TTL-
compatible clock signal. The CLKIN input cannot be halted,
changed during operation or operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC300. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC300
uses an input clock with a frequency equal to half the instruc-
tion rate; a 12.5 MHz input clock yields a 40 ns processor cycle
(which is equivalent to 25 MHz). Normally instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.
Because the ADMC300 includes an on-chip oscillator circuit,
an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in
Figure 4. A parallel-resonant, fundamental frequency, micro-
processor-grade crystal should be used. A clock output signal
(CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency.
Reset
The
RESET signal initiates a master reset of the ADMC300.
The
RESET signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the
RESET signal should be held low. On
any subsequent resets, the
RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
If an RC circuit is used to generate the
RESET signal, the use of
an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis-
ters and performs a full reset of all of the motor control periph-
erals. When the
RESET line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1.
Boot Loading
On power-up or reset, the ADMC300 is configured so that
execution begins at the internal PM ROM at address 0x0800.
This starts execution of the internal monitor function that first
performs some initialization functions and copies a default inter-
rupt vector table to addresses 0x0000–0x005F of program memory
RAM. The monitor next attempts to boot load from an external
SROM or E
2PROM on SPORT1 using the three wire connec-
tion of Figure 4. The monitor program first toggles the RFS1/
SROM pin of the ADMC300 to reset the serial memory device.
If an SROM or E
2PROM is connected to SPORT1, data is
clocked into the ADMC300 at a rate CLKOUT/26. Both


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