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ADMC328YR-XXX-YY データシート(PDF) 10 Page - Analog Devices |
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ADMC328YR-XXX-YY データシート(HTML) 10 Page - Analog Devices |
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10 / 32 page  ADMC328 –10– REV. B SYSTEM INTERFACE Figure 4 shows a basic system configuration for the ADMC328 with an external crystal. ADMC328 XTAL CLKIN 10MHz CLKOUT RESET 22pF 22pF Figure 4. Basic System Configuration Clock Signals The ADMC328 can be clocked either by a crystal or a TTL- compatible clock signal. For normal operation, the CLKIN input cannot be halted, changed during operation, or operated below the specified minimum frequency. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMC328. In this mode, with an external clock signal, the XTAL pin must be left unconnected. The ADMC328 uses an input clock with a frequency equal to half the instruction rate; a 10 MHz input clock yields a 50 ns processor cycle (which is equivalent to 20 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate, which is indicated by the CLKOUT signal when enabled. Because the ADMC328 includes an on-chip oscillator feedback circuit, an external crystal may be used instead of a clock source, as shown in Figure 4. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors as shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output signal (CLKOUT) is generated by the processor at the processor’s cycle rate of twice the input frequency. Reset The ADMC328 DSP core and peripherals must be correctly re- set when the device is powered up to assure proper initialization. The ADMC328 contains an integrated power-on reset (POR) circuit that provides a complete system reset on power-up and power-down. The POR circuit monitors the voltage on the ADMC328 VDD pin and holds the DSP core and peripherals in reset while VDD is less than the threshold voltage level, VRST. When this voltage is exceeded, the ADMC328 is held in reset for an additional 2 16 DSP clock cycles (t RST in Figure 5). On power-down, when the voltage on the VDD pin falls below VRST–VHYST, the ADMC328 will be reset. Also, if the external RESET pin is actively pulled low at any time after power-up, a complete hardware reset of the ADMC328 is initiated. VRST VDD RESET VRST – VHYST tRST Figure 5. Power-On Reset Operation The ADMC328 reset sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT register and performs a full reset of all of the motor control peripherals. Following a power-up, it is possible to initiate a DSP core and motor control peripheral reset by pulling the RESET pin low. The RESET signal must meet the minimum pulsewidth specifi- cation, tRSP. Following the reset sequence, the DSP core starts executing code from the internal PM ROM located at 0x0800. DSP Control Registers The DSP core has a system control register, SYSCNTL, memory mapped at DM (0x3FFF). SPORT1 is configured as a serial port when Bit 10 is set, or as flags and interrupt lines when this bit is cleared. For proper operation of the ADMC328, all other bits in this register must be cleared. The DSP core has a wait state control register, MEMWAIT, memory mapped at DM (0x3FFE). The default value of this register is 0xFFFF. For proper operation of the ADMC328 this register must be set to 0x8000. The configuration of both the SYSCNTL and MEMWAIT registers of the ADMC328 are shown at the end of this data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMC328 is a flexible, pro- grammable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction motors (ACIM) or permanent magnet synchronous motors (PMSM). In addition, the PWM block contains special functions that consid- erably simplify the generation of the required PWM switching patterns for control of electronically commutated motors (ECM) or brushless dc motors (BDCM). The PWM generator produces three pairs of active high PWM signals on the six PWM output pins (AH, AL, BH, BL, CH, and CL). The six PWM output signals consist of three high side drive signals (AH, BH, and CH) and three low side drive signals (AL, BL, and CL). The switching frequency, dead time and minimum pulsewidths of the generated PWM patterns are pro- grammable using respectively the PWMTM, PWMDT, and PWMPD registers. In addition, three registers (PWMCHA, PWMCHB, and PWMCHC) control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG register. In addition, three control bits of the PWMSEG register permit crossover of the two signals of a PWM pair for easy control of ECM or BDCM. In crossover mode, the PWM signal destined for the high side switch is diverted to the complementary low side output, and the signal destined for the low side switch is diverted to the corresponding high side output signal. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation tech- niques: optical isolation using optocouplers, and transformer isolation using pulse transformers. The PWM controller of the ADMC328 permits mixing of the output PWM signals with a high frequency chopping signal to permit an easy interface to such pulse transformers. The features of this gate-drive chop- ping mode can be controlled by the PWMGATE register. There is an 8-bit value within the PWMGATE register that directly |
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