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ADV476KP66 データシート(PDF) 2 Page - Analog Devices |
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ADV476KP66 データシート(HTML) 2 Page - Analog Devices |
2 / 12 page REV. B –2– ADV476–SPECIFICATIONS (VCC = +5 V 10%, IREF = 8.88 mA. All Specifications TMIN to TMAX 1 unless otherwise noted.) Parameter All Versions Units Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) 6 Bits Accuracy (Each DAC) Integral Nonlinearity ±0.5 LSB max Guaranteed Monotonic Full Scale Error ±5 % max Full Scale = 2.15 IREF RL, IREF = 8.39 mA Blank Level ±0.5 LSB max BLANK = Logic Low Offset Error ±0.5 LSB max BLANK = Logic High DIGITAL INPUTS Input High Voltage, VINH 2 V min Input Low Voltage, VINL 0.8 V max Input Current, IIN ±10 µA max VCC = 5.5 V, VIN = 0.4 V to VCC Input Current (RD Input Only) ±100 µA max VCC = 5.5 V, VIN = 0.4 V to VCC Input Capacitance, CIN 7 pF typ DIGITAL OUTPUTS Output High Voltage, VOH 2.4 V min ISOURCE = 500 µA, V CC = 4.5 V Output Low Voltage, VOL 0.4 V max ISINK = 5.0 mA, VCC = 4.5 V Floating-State Leakage Current ±50 µA max VCC = 5.5 V, 0.4 V < VIN < VCC Floating-State Output Capacitance 7 pF typ ANALOG OUTPUTS Max Output Voltage 1.5 V min IO < 10 mA, IO = 2.15 IREF Max Output Current 21 mA min VO ≤ 1 V DAC to DAC Matching 2 ±2.5 % max Analog Output Capacitance 10 pF typ BLANK = Logic Low CURRENT REFERENCE Input Current (IREF) Range –3/–10 mA min/mA max Voltage at IREF VCC –3/VCC V min/V max IREF = 8.88 mA POWER SUPPLY Supply Voltage, VCC 4.5/5.5 V min/V max Supply Current, ICC 220 mA max fMAX = 66 MHz IO = 2.15 IREF, D0–D7 Unloaded Power Supply Rejection Ratio 6 %/V 4.5 < VCC < 5.5 V, IO = 2.15 IREF, RL = 37.5 Ω, CL = 30 pF, IREF = 8.88 mA. DYNAMIC PERFORMANCE Clock and Data Feedthrough 3, 4 –35 dB typ Glitch Impulse 3, 4 75 pV secs typ NOTES 1Temperature range (T MIN to TMAX); 0 to +70°C. 2Relative to the midpoint of the distribution of the three DACs measured at full scale. 3TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out- puts. Analog output load ≤10 pF, 37.5 Ω. D0–D7 output load ≤50 pF. See timing notes in Figure 2. 4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 k Ω resistor to ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2 clock rate. Specifications subject to change without notice. |
同様の部品番号 - ADV476KP66 |
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同様の説明 - ADV476KP66 |
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