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データシートサーチシステム |
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データシートサーチシステム |
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ADV7123JST240 データシート(PDF) 5 Page - Analog Devices |
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ADV7123JST240 データシート(HTML) 5 Page - Analog Devices |
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5 / 20 page  –5– REV. B ADV7123 3.3 V DYNAMIC SPECIFICATIONS Parameter Min Typ Max Unit AC LINEARITY Spurious-Free Dynamic Range to Nyquist 2 Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 67 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 60 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 48 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 57 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 58 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 52 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 41 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 70 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 70 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 65 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 58 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 52 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 61 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 53 dBc Spurious-Free Dynamic Range within a Window Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 77 dBc fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span 64 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 74 dBc fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span 60 dBc Total Harmonic Distortion fCLK = 50 MHz; fOUT = 1.00 MHz TA = 25 °C66 dBc TMIN to TMAX 65 dBc fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 100 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc DAC PERFORMANCE Glitch Impulse 10 pVs DAC Crosstalk3 23 dB Data Feedthrough 4, 5 22 dB Clock Feedthrough 4, 5 33 dB NOTES 1These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. 2Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V REF. 3DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions. 4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5TTL input values are 0 V to 3 V, with input rise/fall times of –3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs. Specifications subject to change without notice. (VAA = 3.0 V–3.6 V 1, V REF = 1.235 V, RSET = 680 , CL = 10 pF. All specifications are TA = 25 C, unless otherwise noted, TJ MAX = 110 C.) |
同様の部品番号 - ADV7123JST240 |
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同様の説明 - ADV7123JST240 |
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