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FW802 データシート(PDF) 5 Page - Agere Systems

部品番号 FW802
部品情報  Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
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FW802 データシート(HTML) 5 Page - Agere Systems

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Data Sheet, Rev. 3
FW802A Low-Power PHY IEEE 1394A-2000
June 2001
Two-Cable Transceiver/Arbiter Device
Agere Systems Inc.
5
Description (continued)
to become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or dis-
connection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
The SYSCLK output will become active (and the PHY/
link interface will be initialized and become operative)
within 3 ms after LPS is asserted high, when the
FW802A is in the low-power mode.
Two of the signals are used to set up various test
conditions used in manufacturing. These signals (SE
and SM) should be connected to VSS for normal
operation.
5-5459.f (F)
Figure 1. Block Diagram
LINK
INTERFACE
I/O
RECEIVED
DATA
DECODER/
ARBITRATION
AND
CONTROL
RETIMER
STATE
MACHINE
LOGIC
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
CABLE PORT 1
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
TRANSMIT
DATA
ENCODER
CABLE PORT 0
TPA0+
TPA0–
TPB0+
TPB0–
TPBIAS0
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
XI
XO
CPS
LPS
/ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
C/LKON
SE
SM
PD
/RESET
CRYSTAL
D4
D5
D6
D7
PC0
PC1
PC2
R0
R1


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