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ADP1051ACPZ-RL データシート(PDF) 6 Page - Analog Devices

部品番号 ADP1051ACPZ-RL
部品情報  Digital Controller for Isolated Power Supply with PMBus Interface
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ホームページ  http://www.analog.com
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ADP1051ACPZ-RL データシート(HTML) 6 Page - Analog Devices

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ADP1051
Preliminary Technical Data
Rev. PrA | Page 6 of 17
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
−4.8
+7.2
mV
From 0% to 100% of valid input voltage
−2.6
+1.6
% FSR
OTP
Threshold Accuracy
T = 85°C with 100 kΩ||16.5 kΩ
−0.9
+0.25
% FSR
−14.4
+4
mV
T = 100°C with 100 kΩ||16.5 kΩ
-0.5
+1.1
% FSR
-8
+17.6
mV
Comparator Speed
10
ms
Temperature Readings According
to Internal Linearization Scheme
Factory trimmed to 46 µA (set Register
0xFE2D to 0xE6); NTC R0 = 100 kΩ, 1%;
beta = 4250 1%; REXT = 16.5 kΩ 1%
T = 25°C to 100°C
7
°C
T = 100°C to 125°C
5
°C
PG/ALT# (OPEN DRAIN) PIN
Output Low Level
VOL
Sinking Current = 10 mA
0.4
V
CTRL, SYNI/FLGI PINS
Input Low Level
VIL
Sinking Current = 10 mA
0.4
V
Input High Level
VIH
VDD − 0.8
V
SDA/SCL PINS
VDD = 3.3 V
Input Voltage Low
VIL
0.8
V
Input Voltage High
VIH
VDD − 1.2
V
Output Voltage Low
VOL
0.4
V
Leakage Current
−5
+5
µA
SERIAL BUS TIMING
Clock Frequency
100
400
kHz
Glitch Immunity
tSW
50
ns
Bus Free Time
tBUF
4.7
µs
Start Setup Time
tSU;STA
4.7
µs
Start Hold Time
tHD;STA
4
µs
SCL Low Time
tLOW
4.7
µs
SCL High Time
tHIGH
4
µs
SCL, SDA Rise Time
tR
1000
ns
SCL, SDA Fall Time
tF
300
ns
Data Setup Time
tSU;DAT
250
ns
Data Hold Time
tHD;DAT
300
ns
EEPROM
EEPROM Update Time
Time from the updating command to
EEPROM updating finish (TJ = 25°C)
40
ms
Reliability
Endurance1
TJ = 85°C
10,000
Cycles
TJ = 125°C
1,000
Cycles
Data Retention2
TJ = 85°C
20
Years
TJ = 125°C
10
Years
1
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
2
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.


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