ADV7125JSTZ330 datasheet(5/16 Pages) AD

部品番号	ADV7125JSTZ330

部品情報	CMOS, 330 MHz Triple 8-Bit High Speed Video DAC

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ADV7125

Rev. C | Page 5 of 16

5 V TIMING SPECIFICATIONS

VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.

Table 3.

Parameter3

Symbol

Min

Typ

Max

Unit

Conditions

ANALOG OUTPUTS

Analog Output Delay

t6

5.5

ns

Analog Output Rise/Fall Time4

t7

1.0

ns

Analog Output Transition Time5

t8

15

ns

Analog Output Skew6

t9

1

2

ns

CLOCK CONTROL

CLOCK Frequency7

fCLK

0.5

50

MHz

50 MHz grade

0.5

140

MHz

140 MHz grade

0.5

240

MHz

240 MHz grade

Data and Control Setup6

t1

0.5

ns

Data and Control Hold6

t2

1.5

ns

CLOCK Period

t3

4.17

ns

CLOCK Pulse Width High6

t4

1.875

ns

fCLK_MAX = 240 MHz

CLOCK Pulse Width Low6

t5

1.875

ns

fCLK_MAX = 240 MHz

CLOCK Pulse Width High6

t4

2.85

ns

fCLK_MAX = 140 MHz

CLOCK Pulse Width Low6

t5

2.85

ns

fCLK_MAX = 140 MHz

CLOCK Pulse Width High

t4

8.0

ns

fCLK_MAX = 50 MHz

CLOCK Pulse Width Low

t5

8.0

ns

fCLK_MAX = 50 MHz

Pipeline Delay6

tPD

1.0

Clock cycles

PSAVE Up Time6

t10

2

10

ns

1 The maximum and minimum specifications are guaranteed over this range.

2 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.

3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.

4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.

5 Measured from 50% point of full-scale transition to 2% of final value.

6 Guaranteed by characterization.

7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.

同様の部品番号 - ADV7125JSTZ330

メーカー	部品番号	データシート	部品情報
Analog Devices	ADV7125JSTZ330	410Kb / 17P	CMOS, 330 MHz Triple 8-Bit High Speed Video DAC

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