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74ALVC162374 データシート(PDF) 2 Page - Fairchild Semiconductor |
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74ALVC162374 データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Connection Diagram Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP Functional Description The 74ALVC162374 consists of sixteen edge-triggered flip- flops with individual D-type inputs and 3-STATE true out- puts. The device is byte controlled with each byte function- ing identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip- flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. Logic Diagram Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs CP1 OE1 I0–I7 O0–O7 LH H LL L LL X O0 XH X Z Inputs Outputs CP2 OE2 I8–I15 O8–O15 LH H LL L LL X O0 XH X Z |
同様の部品番号 - 74ALVC162374 |
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同様の説明 - 74ALVC162374 |
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