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74F251APC データシート(PDF) 2 Page - Fairchild Semiconductor |
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74F251APC データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description This device is a logical implementation of a single-pole, 8- position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Z = OE •(I 0•S0•S1 •S2 + I1•S0•S 1•S2 + I2•S0•S1•S2 + I3•S0•S1•S2 + I4•S0•S1•S2 + I5•S0•S1•S2 + I6•S0•S1•S2 + I7•S0•S1•S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multi- plexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high imped- ance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltages. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0–S2 Select Inputs 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA I0–I7 Multiplexer Inputs 1.0/1.0 20 µA/−0.6 mA Z 3-STATE Multiplexer Output 150/40 (33.3) −3 mA/24 mA (20 mA) Z Complementary 3-STATE Multiplexer Output 150/40 (33.3) −3 mA/24 mA (20 mA) Inputs Outputs OE S2 S1 S0 Z Z HX X X Z Z LL LL I0 I0 LL L H I1 I1 LL H L I2 I2 LL H H I3 I3 LH L L I4 I4 LH L H I5 I5 LH H L I6 I6 L HHH I7 I7 |
同様の部品番号 - 74F251APC |
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同様の説明 - 74F251APC |
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