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FOD3182SV データシート(PDF) 7 Page - Fairchild Semiconductor |
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FOD3182SV データシート(HTML) 7 Page - Fairchild Semiconductor |
7 / 23 page ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 7 Notes: 1. Derate linearly above +79°C free air temperature at a rate of 0.37mA/°C. 2. Maximum pulse width = 10µs, maximum duty cycle = 11%. 3 Derate linearly above +79°C, free air temperature at the rate of 5.73mW/°C. 4. No derating required across operating temperature range. 5. In this test, VOH is measured with a dc load current of 100mA. When driving capacitive load VOH will approach VDD as IOH approaches zero amps. 6. Maximum pulse width = 1ms, maximum duty cycle = 20%. 7. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal. 8. PWD is defined as | tPHL – tPLH | for any given device. 8. The difference between tPHL and tPLH between any two FOD3182 parts under same operating conditions, with equal loads. 10. Pin 1 and 4 need to be connected to LED common. 11. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse VCM to assure that the output will remain in the high state (i.e. VO > 15V). 12. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. VO < 1.0V). 13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000Vrms, 60Hz for 1 second (leakage detection current limit II-O < 10µA). 14. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. |
同様の部品番号 - FOD3182SV |
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同様の説明 - FOD3182SV |
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