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SMUN5330DW1T1G データシート(PDF) 1 Page - ON Semiconductor |
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SMUN5330DW1T1G データシート(HTML) 1 Page - ON Semiconductor |
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1 / 34 page  © Semiconductor Components Industries, LLC, 2012 March, 2014 − Rev. 14 1 Publication Order Number: MUN5311DW1T1/D MUN5311DW1T1G, SMUN5311DW1T1G, NSVMUN5311DW1T1G Series Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the MUN5311DW1T1G series, two complementary BRT devices are housed in the SOT−363 package which is ideal for low power surface mount applications where board space is at a premium. Features • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • Available in 8 mm, 7 inch/3000 Unit Tape and Reel • S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant* MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2, − minus sign for Q1 (PNP) omitted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOT−363 CASE 419B STYLE 1 MARKING DIAGRAM ORDERING AND DEVICE MARKING INFORMATION See detailed ordering, shipping, and specific marking information in the table on page 2 of this data sheet. Q1 R1 R2 R2 R1 Q2 (1) (2) (3) (4) (5) (6) http://onsemi.com http://onsemi.com xx M G G 1 6 (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. xx = Device Code M = Date Code* G = Pb−Free Package |
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