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74LVTH273SJ データシート(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH273SJ データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Transition Oo Previous Oo before HIGH-to-LOW of CP Functional Description The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig- nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input CLR Clear O0–O7 Outputs Inputs Outputs Dn CP CLR On H HH L HL XH or L H Oo XX L L |
同様の部品番号 - 74LVTH273SJ |
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同様の説明 - 74LVTH273SJ |
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