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ACE25C512 データシート(PDF) 8 Page - ACE Technology Co., LTD. |
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ACE25C512 データシート(HTML) 8 Page - ACE Technology Co., LTD. |
8 / 34 page ACE25C512 512K-BIT Serial Flash Memory VER 1.2 8 WIP Bit WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in “12.6 AC Electrical Characteristics”). When the program, erase or write status register (or security sector) instruction has completed, the WIP bit will be cleared to a 0 state indicating the device is ready for further instructions. Write Enable Latch bit (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register. Block Protect Bits (BP2, BP1,BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in “12.6 AC Electrical Characteristics”). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Table 2 Status Register Memory Protection). The factory default setting for the Block Protection Bits is 0, none of the array protected. Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Table 2 Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. Status Register Protect bit / Lock_bit (SRP/LB) The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect ( WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. In OTP mode, this bit is served as Lock_bit (LB), user can read/program/erase sec urity sector as normal sector while LB value is equal 0, after LB is programmed with 1 by WRSR command, the security sector is protected from program and erase operation. The LB can only be programmed once. Note: In OTP mode, the WRSR command will ignore any input data and program LB to 1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command to lock the security sector before leaving OTP mode. |
同様の部品番号 - ACE25C512 |
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同様の説明 - ACE25C512 |
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