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DM74LS126AN データシート(PDF) 1 Page - Fairchild Semiconductor

部品番号 DM74LS126AN
部品情報  Quad 3-STATE Buffer
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM74LS126AN データシート(HTML) 1 Page - Fairchild Semiconductor

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© 2000 Fairchild Semiconductor Corporation
DS006388
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS126A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned OFF presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
= A
H
= HIGH Logic Level
L
= LOW Logic Level
X
= Either LOW or HIGH Logic Level
Hi-Z
= 3-STATE (Outputs are disabled)
Order Number
Package Number
Package Description
DM74LS126AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS126AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
AC
Y
LH
L
HH
H
X
L
Hi-Z


同様の部品番号 - DM74LS126AN

メーカー部品番号データシート部品情報
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同様の説明 - DM74LS126AN

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