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FAN5231 データシート(PDF) 8 Page - Fairchild Semiconductor |
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FAN5231 データシート(HTML) 8 Page - Fairchild Semiconductor |
8 / 17 page FAN5231 8 REV. 1.1.1 8/15/01 The ‘11111’ and ‘0111‘VID codes, as shown in Table 1, shut the IC down and set PGOOD low. Table 1. Note: 1. 0 = connected to GND or VSS, 1 = open or connected to 3.3V through pull-up resistors. Core Converter PWM Operation At the nominal current core converter operates in a fixed frequency PWM mode. The output voltage is compared with a reference voltage set by the DAC. The derived error signal is amplified by an internally compensated error amplifier and applied to the inverting input of the PWM comparator. To provide output voltage droop for enhanced dynamic load regulation, a signal proportional to the output current is added to the voltage feedback signal. This feedback scheme in conjunction with a PWM ramp proportional to the input voltage allows for fast and stable loop response over a wide range of input voltage and output current variations. For the sake of efficiency and maximum simplicity, the current sense signal is derived from the voltage drop across the lower MOSFET during its conduction time. Mode-Compensated Droop An output voltage "droop" or an active voltage positioning is now widely used in the computer power applications. The technique is based on raising the converter voltage at light load in anticipation of the possible load current step. Con- versely, the output voltage is lowered at high load in antici- pation of possible load drop. The output voltage varies with the load like it is a resistor connected in series with the con- verter’s output. When done as part of the feedback in a closed loop, the "droop" is not associated with substantial power losses, though. There is no such resistor in a real cir- cuit, but rather the feature is emulated by the feedback. The "droop" allows a reduction in size and cost of the output capacitors required to handle the transient. Additionally to that, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even slight voltage decrease translates in a measurable reduction in power dissipated. Figure 3. Mode-Compensated Droop When powering the dual mode processor, it is desired to have an adequate "droop" (equal fractions of the pro- grammed output voltage) in both performance and battery- optimized modes of operation. The traditional "droop" is normally tuned to the worse case load, which is associated with the performance mode. In the battery optimized mode, the CPU operating voltage and the clock frequency are both scaled down. Due to the constant gain in the current loop, the traditional "droop" compensates only for the operating volt- age change. The degree of the droop achieved in this case is Pin Name Nominal OUT1 Voltage VID4 VID3 VID2 VID1 VID0 00000 2.00 0000 1 1.95 0 0 0 1 0 1.90 0 0 0 1 1 1.85 00100 1.80 00101 1.75 00110 1.70 00111 1.65 01000 1.60 01001 1.55 01010 1.50 01011 1.45 01100 1.40 01101 1.35 01110 1.30 0 1 1 1 1 No CPU* 10000 1.275 10001 1.250 10010 1.225 10011 1.200 10100 1.175 10101 1.150 10110 1.125 10111 1.100 11000 1.075 11001 1.050 11010 1.025 11011 1.000 11100 0.975 11101 0.950 11110 0.925 11111 No CPU* 0 5 10 1.6 1.35 Traditional Droop Mode-Compensated Droop ICPU VCPU Performance Mode Battery-Optimized Mode |
同様の部品番号 - FAN5231 |
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同様の説明 - FAN5231 |
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