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FAN5231 データシート(PDF) 9 Page - Fairchild Semiconductor |
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FAN5231 データシート(HTML) 9 Page - Fairchild Semiconductor |
9 / 17 page FAN5231 REV. 1.1.1 8/15/01 9 not the same because the CPU current is significantly lower as it is illustrated by the following equaton. ICPU = KCPU • VCPUi • FCPUi • KF; Where, KCPU — is a processor constant; VCPUi — is proces- sor operating voltage; FCPUi — is processor clock frequency; KF — is a coefficient that varies from 0 to 1 and indicates how heavily processor is engaged by the software; i — is a denominator associated with the processor mode of opera- tion (performance or battery optimized). Figure 4. This leads to deterioration of the droop benefits in the battery-optimized mode where they are mostly appreciable, Fig. 3. Figure 5. The FAN5231 incorporates a new proprietary droop technique specially designed for the SpeedStep-enabled converters and provides mode-compensated, relatively equal droop in both, the performance and the battery-optimized modes. The droop is set as a fraction of the VID programmed voltage and the gain in the current loop is different for each VID combination, those providing the droop, which is compensated for the voltage and the frequency changes associated with the different CPU modes of operation. Figure 6. To accommodate the droop the output voltage of core converter is raised 2% at no load conditions. The resistor connected to ISEN1 pin programs the amount of droop. This resistor sets the gain in the current feedback loop. The droop is scaled to 5.5% of the VID code when current into ISEN1 pin equals 75µA. The output voltage waveforms with droop subjected to load step are shown on Fig. 4–Fig. 6 . Feedback Loop Compensation Due to implemented average current mode control, the modulator has a single pole response with -1 slope at frequency determined by load where Ro – is load resistance, Co – is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufficient. To reduce number of external components and remove the burden at determining compensation components from a system designer, both PWM controllers have internally compensated error amplifiers. Figure 7 shows Type 2 amplifier and its response along with responses of current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero- pole pair that causes a flat gain region at frequencies in between the zero and the pole. Ch1 50mV Ch2 5.0A M50µs 1 2 VCPU=1.6V ICPU =0.3A>>18A Ch1 50mV Ch2 5.0A M50µs 1 2 VCPU=1.35V ICPU = 0.3A>>13 .5A Ch1 50mV Ch2 5.0A M50µs 1 2 VCPU=1.00V I CPU =0.3A>>12.0A RCS IMAX RDS ON () ⋅ 75 µA -------------------------------------- = FPO 1 2 π R 0 C 0 ⋅⋅ ---------------------------- = ’ FZ 1 2 π R 2 C 1 ⋅⋅ ---------------------------- 6 kHz = = ; FP 1 2 π R 2 C 1 ⋅⋅ ---------------------------- 600 kHz = = ; |
同様の部品番号 - FAN5231 |
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同様の説明 - FAN5231 |
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