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AD6650 データシート(PDF) 5 Page - Analog Devices |
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AD6650 データシート(HTML) 5 Page - Analog Devices |
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5 / 44 page  AD6650 Rev. A | Page 5 of 44 ELECTRICAL CHARACTERISTICS Table 3. Parameter (Conditions) Temp Test Level Min Typ Max Unit LOGIC INPUTS Logic Compatibility Full IV 3.3 V CMOS Digital Logic Logic 1 Voltage Full IV 2.0 VDD V Logic 0 Voltage Full IV 0 0.8 V Logic 1 Current 25°C V 60 μA Logic 0 Current 25°C V 7 μA Input Capacitance 25°C V 5 pF CLOCK INPUTS Differential Input Voltage1 25°C V 0.4 3.6 V p-p Common-Mode Input Voltage 25°C V DVDD/2 V Differential Input Resistance 25°C V 7.5 kΩ Differential Input Capacitance 25°C V 5 pF LOGIC OUTPUTS Logic Compatibility Full 3.3 V CMOS/TTL Logic 1 Voltage (IOH = 0.25 mA) Full IV 2.4 VDD − 0.2 V Logic 0 Voltage (IOL = 0.25 mA) Full IV 0.2 0.8 V IDD SUPPLY CURRENT CLK = 52 MHz (GSM Example) IDVDD Full VII 155 mA IAVDD Full VII 360 mA POWER DISSIPATION CLK = 52 MHz (GSM/EDGE Example) Full VII 1.7 2.1 W 1 All ac specifications are tested by driving CLK and CLK differentially. GENERAL TIMING CHARACTERISTICS Table 4. Parameter (Conditions) Symbol Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS CLK Period1 tCLK Full I 9.6 19.2 ns CLK Width Low tCLKL Full IV 0.5 × tCLK ns CLK Width High tCLKH Full IV 0.5 × tCLK ns RESET TIMING REQUIREMENTS RESET Width Low tSSF Full IV 30 ns PIN_SYNC TIMING REQUIREMENTS SYNC to ↑ CLK Setup Time tSS Full IV −3 ns SYNC to ↑ CLK Hold Time tHS Full IV 6 ns SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS2 ↑ CLK to ↑ SCLK Delay (Divide-by-1) tDSCLK1 Full IV 3.2 12.5 ns ↑ CLK to ↑ SCLK Delay (For Any Other Divisor) tDSCLKH Full IV 4.4 16 ns ↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number) tDSCLKL Full IV 4.7 16 ns ↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number) tDSCLKLL Full IV 4 14 ns ↑ SCLK to SDFS Delay tDSDFS Full IV 1 2.6 ns ↑ SCLK to SDO0 Delay tDSDO0 Full IV 0.5 3.5 ns ↑ SCLK to SDO1 Delay tDSDO1 Full IV 0.5 3.5 ns ↑ SCLK to DR Delay tDSDR Full IV 1 3.5 ns 1 Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a 52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS. 2 The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1. |
同様の部品番号 - AD6650_07 |
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同様の説明 - AD6650_07 |
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