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ADF4001BRU-REEL7 データシート(PDF) 1 Page - Analog Devices |
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ADF4001BRU-REEL7 データシート(HTML) 1 Page - Analog Devices |
1 / 17 page a ADF4001 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc. All rights reserved. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. REV. 200 MHz Clock Generator PLL FUNCTIONAL BLOCK DIAGRAM RFINA RFINB 13-BIT N COUNTER LOCK DETECT CURRENT SETTING 1 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 M1 M3 M2 SDOUT AVDD REFIN CLK DATA LE AVDD DVDD VP CPGND RSET 14-BIT R COUNTER R COUNTER LATCH FUNCTION LATCH 24-BIT INPUT REGISTER N COUNTER LATCH SDOUT 22 14 ADF4001 MUXOUT MUX HIGH Z CURRENT SETTING 2 CHARGE PUMP CP CE AGND DGND PHASE FREQUENCY DETECTOR REFERENCE 13 FEATURES 200 MHz Bandwidth 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware Compatible to the ADF4110/ADF4111/ ADF4112/ADF4113 Typical Operating Current 4.5 mA Ultralow Phase Noise 16-Lead TSSOP 20-Lead LFCSP APPLICATIONS Clock Generation Low Frequency PLLs Low Jitter Clock Source Clock Smoothing Frequency Translation SONET, ATM, ADM, DSLAM, SDM GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an exter- nal loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation. 2013 781/461-3113 B |
同様の部品番号 - ADF4001BRU-REEL7 |
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同様の説明 - ADF4001BRU-REEL7 |
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