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ADRF6806ACPZ-R7 データシート(PDF) 8 Page - Analog Devices

部品番号 ADRF6806ACPZ-R7
部品情報  50 MHz to 525 MHz Quadrature Demodulator with Fractional-N PLL and VCO
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ADRF6806ACPZ-R7 データシート(HTML) 8 Page - Analog Devices

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ADRF6806
Data Sheet
Rev. B | Page 8 of 36
Pin No.
Mnemonic
Description
8
MUXOUT
Multiplexer Output. This output can be programmed to provide the reference output signal or the
lock detect signal. The output is selected by programming the appropriate register.
9
DECL2
Connect a 0.1 μF capacitor between this pin and ground.
10
VCC2
The 3.3 V power supply for the 2.5 V LDO.
12
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14
LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
17, 34
VCCLO
The 3.3 V power supply for the LO path blocks.
18, 19
QBBP, QBBN
Demodulator Q-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
22
VCCBB
The 5 V power supply for the demodulator blocks.
23
VOCM
Baseband Common-Mode Reference Input; 1.65 V nominal. It sets the dc common-mode level of
the IBBx and QBBx outputs.
25, 26
RFIP, RFIN
Differential 100 Ω, Internally Biased RF Inputs. These pins must be ac-coupled.
28
VCCRF
The 5 V power supply for the demodulator blocks.
29
DECL3
Connect a 2.2 μF capacitor between this pin and ground.
32, 33
IBBN, IBBP
Demodulator I-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
36
LOSEL
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set
low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally
applied LO drive must be at M×LO frequency (where M corresponds to the main LO divider setting). LON
and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and
the LXL bit of Register 5 (DB4) low. The output frequency is controlled by the LO output divider bits
in Register 7. This pin should not be left floating.
37, 38
LON, LOP
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to
the main divider setting). (Differential Input/Output Impedance of 50 Ω)
39
VTUNE
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
40
DECL1
Connect a 10 μF capacitor between this pin and ground as close to the device as possible because
this pin serves as the VCO supply and loop filter reference.
EP
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.


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