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AD5308BRUZ-REEL7 データシート(PDF) 15 Page - Analog Devices |
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AD5308BRUZ-REEL7 データシート(HTML) 15 Page - Analog Devices |
15 / 28 page AD5308/AD5318/AD5328 Rev. F | Page 15 of 28 THEORY OF OPERATION The AD5308/AD5318/AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains eight output buffer ampli- fiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. DAC A, DAC B, DAC C, and DAC D share a common reference input, VREFABCD. DAC E, DAC F, DAC G, and DAC H share a common reference input, VREFEFGH. Each reference input can be buffered to draw virtually no current from the reference source, can be unbuffered to give a reference input range from 0.25 V to VDD, or can come from VDD. The devices have a power-down mode in which all DACs can be turned off individually with a high impedance output. DIGITAL-TO-ANALOG CONVERTER The architecture of one DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corre- sponding DAC. Figure 29 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by N REF OUT D V V 2 × = where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 255 for AD5308 (8 bits) 0 to 1023 for AD5318 (10 bits) 0 to 4095 for AD5328 (12 bits) N is the DAC resolution. INPUT REGISTER OUTPUT BUFFER AMPLIFIER REFERENCE BUFFER GAIN MODE (GAIN = +1 OR +2) VOUTA VREFABCD VDD BUF RESISTOR STRING DAC REGISTER VDD Figure 29. Single DAC Channel Architecture DAC Reference Inputs There is a reference pin for each quad of DACs. The reference inputs can be buffered from VDD, or unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to the headroom and footroom of the reference amplifier. If there is a buffered reference in the circuit (for example, the REF192), there is no need to use the on-chip buffers of the AD5308/AD5318/AD5328. In unbuffered mode, the input impedance is still large at typically 45 kΩ per reference input for 0 V to VREF mode and 22 kΩ for 0 V to 2 VREF mode. RESISTOR STRING The resistor-string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. R R R R R TO OUTPUT AMPLIFIER Figure 30. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, the gain of the output amplifier, the offset error, and the gain error. If a gain of 1 is selected (gain bit = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (gain bit = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD − 0.001 V. The output amplifier is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in Figure 14. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 μs. |
同様の部品番号 - AD5308BRUZ-REEL7 |
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同様の説明 - AD5308BRUZ-REEL7 |
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