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DAC0832LCWM データシート(PDF) 5 Page - Texas Instruments |
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DAC0832LCWM データシート(HTML) 5 Page - Texas Instruments |
5 / 29 page DAC0830, DAC0832 www.ti.com SNAS534B – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. (1) For all other limits TA=25°C. VCC=12 VDC±5% VCC=5 VCC=15.75 VDC VCC=4.75 VDC to 15 VDC ±5% VDC±5% See Limit Symbol Parameter Conditions Note Units Tested Tested Design Typ(2) Design Limit(4) Typ(2) Limit(3) Limit(3) Limit(4) AC CHARACTERISTICS(5) ts Current Setting VIL=0V, VIH=5V 1.0 1.0 μs Time tW Write and XFER VIL=0V, VIH=5V See( 100 250 375 600 5) Pulse Width Min See( 320 320 900 900 1) tDS Data Setup Time VIL=0V, VIH=5V See( 100 250 375 600 1) Min 320 320 900 900 tDH Data Hold Time VIL=0V, VIH=5V See( 30 50 ns 1) Min 30 50 tCS Control Setup VIL=0V, VIH=5V See( 110 250 600 900 Time 1) Min 320 320 1100 1100 tCH Control Hold Time VIL=0V, VIH=5V See( 0 0 0 10 0 1) Min 0 0 (1) Boldface tested limits apply to the LJ and LCJ suffix parts only. (2) Typicals are at 25°C and represent most likely parametric norm. (3) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). (4) Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels. (5) The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply. Switching Waveform Definition of Package Pinouts Control Signals (All control signals level actuated) CS: Chip Select (active low). The CS in combination with ILE will enable WR1. ILE: Input Latch Enable (active high). The ILE in combination with CS enables WR1. WR1: Write 1. The active low WR1 is used to load the digital input data bits (DI) into the input latch. The data in the input latch is latched when WR1 is high. To update the input latch–CS and WR1 must be low while ILE Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DAC0830 DAC0832 |
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