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AD5308WARUZ-REEL7 データシート(Datasheet) 6 Page - Analog Devices

部品番号. AD5308WARUZ-REEL7
部品情報  2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
ダウンロード  28 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5308/AD5318/AD5328
Rev. F | Page 6 of 28
Table 3. Timing Characteristics1, 2, 3
A, B Version
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +105°C
15
ns min
SYNC to SCLK falling edge setup time; temperature range (A, B
verstion): −40°C to +125°C
t5
5
ns min
Data set up time
t6
4.5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
50
ns min
Minimum SYNC high time
t9
20
ns min
LDAC pulse width
t10
20
ns min
SCLK falling edge to LDAC rising edge
t11
0
ns min
SCLK falling edge to LDAC falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
SCLK
DIN
DB15
DB0
t1
t2
t8
t3
t4
t5
t6
t9
t11
t7
t10
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
LDAC1
LDAC2
SYNC
Figure 2. Serial Interface Timing Diagram




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