データシートサーチシステム |
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TLV2322IDR データシート(PDF) 3 Page - Texas Instruments |
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TLV2322IDR データシート(HTML) 3 Page - Texas Instruments |
3 / 33 page TLV2322, TLV2322Y, TLV2324, TLV2324Y LinCMOS ™ LOW-VOLTAGE LOW-POWER OPERATIONAL AMPLIFIERS SLOS187 – FEBRUARY 1997 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV2324Y chip information This chip, when properly assembled, display characteristics similar to the TLV2324. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS + – 1OUT 1IN + 1IN – VDD (4) (6) (3) (2) (5) (1) 2IN + 2IN – 2OUT (11) VDD– /GND + – 3OUT 3IN + 3IN – (13) (10) (9) (12) (8) – + (14) 4OUT 4IN + 4IN – + – (7) CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (12) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. 68 108 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) |
同様の部品番号 - TLV2322IDR |
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同様の説明 - TLV2322IDR |
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