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FM31L278 データシート(PDF) 4 Page - Cypress Semiconductor

部品番号 FM31L278
部品情報  3V Integrated Processor Companion with F-RAM
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM31L278 データシート(HTML) 4 Page - Cypress Semiconductor

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FM33256B SPI Companion w/ FRAM
Document Number: 001-86213 Rev. **
Page 4 of 30
Overview
The FM33256B device combines a serial nonvolatile
RAM with a real-time clock (RTC) and a processor
companion. The companion is a highly integrated
peripheral including a processor supervisor, analog
comparator, a nonvolatile counter, and a serial
number.
The
FM33256B
integrates
these
complementary
but
distinct
functions
under
a
common interface in a single package. The product is
organized as two logical devices. The first is a
memory and the second is the companion which
includes all the remaining functions. From the system
perspective they appear to be two separate devices
with unique op-codes on the serial bus.
The memory is organized as a standalone nonvolatile
SPI memory using standard op-codes. The real-time
clock and supervisor functions are accessed under
their own op-codes. The clock and supervisor
functions are controlled by 30 special function
registers. The RTC/alarm and some control registers
are maintained by the power source on the VBAK
pin, allowing them to operate from battery or backup
capacitor power when VDD drops below a set
threshold. Each functional block is described below.
Memory Operation
The FM33256B is available with 256Kb of memory.
The device uses two-byte addressing for the memory
portion of the chip. This makes the device software
compatible with its standalone memory counterparts,
such as the FM25W256.
Memory is organized in bytes. The 256Kb memory is
32,768 x 8. The memory is based on F-RAM
technology. Therefore it can be treated as RAM and
is read or written at the speed of the SPI bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The SPI protocol is described
on page 18.
The memory array can be write-protected by
software. Two bits (BP0, BP1) in the Status Register
control the protection setting. Based on the setting,
the protected addresses cannot be written. The Status
Register & Write Protection is described in more
detail on page 20.
Processor Companion
In addition to nonvolatile RAM, the FM33256B
incorporates a real-time clock with alarm and highly
integrated processor companion. The companion
includes a low-VDD reset, a programmable watchdog
timer,
a
16-bit
nonvolatile
event
counter,
a
comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic
functions: Detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. The FM33256B has a reset pin (/RST) to
drive a processor reset input during power faults,
power-up, and software lockups. It is an open drain
output with a weak internal pull-up to VDD. This
allows other reset sources to be wire-OR‟d to the
/RST pin. When VDD is above the programmed trip
point, /RST output is pulled weakly to VDD. If VDD
drops below the reset trip point voltage level (VTP),
the /RST pin will be driven low. It will remain low
until VDD falls too low for circuit operation which is
the VRST level. When VDD rises again above VTP,
/RST continues to drive low for at least 50 ms (tRPU)
to ensure a robust system reset at a reliable VDD level.
After tRPU has been met, the /RST pin will return to
the weak high state. While /RST is asserted, serial
bus activity is locked out even if a transaction
occurred as VDD dropped below VTP. A memory
operation started while VDD is above VTP will be
completed internally.
Table 1 below shows how bits VTP(1:0) control the
trip point of the low-VDD reset. They are located in
register 18h, bits 0 and 1. The reset pin will drive
low when VDD is below the selected VTP voltage, and
the SPI interface and F-RAM array will be locked
out. Figure 2 illustrates the reset operation in
response to a low VDD.
Table 1.
VTP Setting
VTP1
VTP0
2.6V
0
0
2.75V
0
1
2.9V
1
0
3.0V
1
1


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