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DAC3174IRGC25 データシート(PDF) 7 Page - Texas Instruments

部品番号 DAC3174IRGC25
部品情報  Dual 14-bit 500 MSPS Digital to Analog Converter
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DAC3174IRGC25 データシート(HTML) 7 Page - Texas Instruments

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SLAS837A – APRIL 2013 – REVISED MAY 2013
PIN ASSIGNMENT TABLE – DUAL BUS MODE (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DATA INTERFACE
DA[6:0]P/N
9/10-
I
LVDS positive input data bits for channel A. Each positive/negative LVDS pair has an internal 100
Ω
19/20
termination resistor. Data format relative to DA_CLKP/N clock is Double Data Rate (DDR) with two
data transfers per DA_CLKP/N clock cycle.
22/23
The data format is 7 MSBs (rising edge)/7 LSBs falling edge.
In the default mode (reverse bus not enabled):
D6P/N is most significant data bit (MSB)
D0P/N is most significant data bit (LSB)
DB[6:0]P/N
26/27
I
LVDS positive input data bits for channel B. Each positive/negative LVDS pair has an internal 100
Ω
termination resistor. Data format relative to DB_CLKP/N clock is Double Data Rate (DDR) with two
29/30-
data transfers per DB_CLKP/N clock cycle.
39/40
The data format is 7 MSBs (rising edge)/7 LSBs falling edge.
In the default mode (reverse bus not enabled):
D6P/N is most significant data bit (MSB)
D0P/N is most significant data bit (LSB)
DA_CLKP/N
6/7
I
DDR differential input data clock for channel A. Edge to center nominal timing.
DB_CLKP/N
24/25
I
DDR differential input data clock for channel B. Edge to center nominal timing.
OUTPUT/CLOCK
DACCLKP/N
½
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
IOUTAP/N
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTAP pin. The IOUTAN
pin is the complement of IOUTAP.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTBP pin. The IOUTBN
pin is the complement of IOUTBP.
REFERENCE
EXTIO
58
I/O
Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
57
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960
Ω resistor to GND.
POWER SUPPLY
IOVDD
45
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
CLKVDD18
3
I
1.8V clock supply
DIGVDD18
21, 28
I
1.8V digital supply. Also supplies LVDS receivers.
VDDA18
50, 64
I
Analog 1.8V supply
VDDA33
55, 56,
I
Analog 3.3V supply
59
VFUSE
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
NC
4, 5
Not used. In actual application, Pins 51, 52, 62 and 63 can be left open or tied to GROUND. It is
51, 52
recommended to tie Pins 4 and 5 to DIGVDD18 and GROUND , respectively.
62, 63
Copyright © 2013, Texas Instruments Incorporated
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