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74LVC1G19GW データシート(PDF) 1 Page - NXP Semiconductors |
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74LVC1G19GW データシート(HTML) 1 Page - NXP Semiconductors |
1 / 18 page 1. General description The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V CC =3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 Cto+85 C and 40 C to +125 C. 74LVC1G19 1-of-2 decoder/demultiplexer Rev. 6 — 6 December 2011 Product data sheet |
同様の部品番号 - 74LVC1G19GW |
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同様の説明 - 74LVC1G19GW |
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