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AD5791BRUZ データシート(PDF) 4 Page - Analog Devices |
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AD5791BRUZ データシート(HTML) 4 Page - Analog Devices |
4 / 28 page AD5791 Data Sheet Rev. D | Page 4 of 28 A, B Version1 Parameter Min Typ Max Unit Test Conditions/Comments Midscale Glitch Impulse8 3.1 nV-sec VREFP = +10 V, VREFN = −10 V 1.7 nV-sec VREFP = 10 V, VREFN = 0 V 1.4 nV-sec VREFP = 5 V, VREFN = 0 V MSB Segment Glitch Impulse8 9.1 nV-sec VREFP = +10 V, VREFN = −10 V, see Figure 42 3.6 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 43 1.9 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 44 Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp Digital Feedthrough 0.4 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output Clamped to Ground) 6 kΩ Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate REFERENCE INPUTS3 VREFP Input Range 5 VDD − 2.5 V V VREFN Input Range VSS + 2.5 V 0 DC Input Impedance 5 6.6 kΩ VREFP, VREFN, code dependent, typical at midscale code Input Capacitance 15 pF VREFP, VREFN LOGIC INPUTS3 Input Current9 −1 +1 µA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF LOGIC OUTPUT (SDO)3 Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA Output High Voltage, VOH IOVCC − 0.5 V V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA High Impedance Leakage Current ±1 µA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOVCC VDD 7.5 VSS + 33 V VSS VDD − 33 −2.5 V VCC 2.7 5.5 V IOVCC 1.71 5.5 V IOVCC ≤ VCC IDD 4.2 5.2 mA ISS 4 4.9 mA ICC 600 900 µA IOICC 52 140 µA SDO disabled DC Power Supply Rejection Ratio3, 10 ±0.6 µV/V VDD ± 10%, VSS = 15 V ±0.6 µV/V VSS ± 10%, VDD = 15 V AC Power Supply Rejection Ratio3 95 dB VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V 95 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V 1 Temperature range: −40°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V. 2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer. 3 Guaranteed by design and characterization, not production tested. 4 Valid for all voltage reference spans. 5 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified. 6 AD5791 configured in X2 gain mode, 25 pF compensation capacitor on AD797. 7 Includes noise contribution from AD8676BRZ voltage reference buffers. 8 The AD5791 is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF.(total capacitance seen by the output buffer, lead capacitance, and so forth). 9 Current flowing in an individual logic pin. 10 Includes PSRR of AD8676BRZ voltage reference buffers. |
同様の部品番号 - AD5791BRUZ |
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同様の説明 - AD5791BRUZ |
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