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HCPL-5400 データシート(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED

部品番号 HCPL-5400
部品情報  Hermetically Sealed, Very High Speed, Logic Gate Optocouplers High radiation immunity
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メーカー  AVAGO [AVAGO TECHNOLOGIES LIMITED]
ホームページ  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

HCPL-5400 データシート(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED

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MIL-PRF-38534 Class H, Class K, and DLA SMD Test Program
the amount of time required for a system’s output to
change from a Logic 1 to a Logic 0, when given a stimulus
at the input (see Figure 5).
When tPLH and tPHL differ in value, pulse width distortion
results. Pulse width distortion is defined as |tPHL- tPLH| and
determines the maximum data rate capability of a dis-
tortion-limited system. Maximum pulse width distortion
on the order of 25-35% is typically used when specifying
the maximum data rate capabilities of systems. The exact
figure depends on the particular application (RS-232,
PCM, T-1, etc.).
These high performance optocouplers offer the advan-
tages of specified propagation delay (tPLH, tPHL), and pulse
width distortion (|tPLH-t PHL|) over temperature and power
supply voltage ranges.
Figure 13. Recommended HCPL-5400 interface circuit
Applications
GND
VCC
HCPL-5400
226
Ω
VCC1 = +5 V
TTL
LSTTL
STTL
HCMOS
TOTEM
POLE
OUTPUT GATE
(e.g. 54AS1000)
DATA
OUT
2
DATA
IN
1
GND 2
Y
0.1
μF
274
Ω
30 pF
A
GND 1
Y = A
VCC2 = 5 V
Figure 14. Alternative HCPL-5400 interface circuit
GND
VCC
HCPL-5400
464
Ω
VCC1 = +5 V
TTL
LSTTL
STTL
OPEN
COLLECTOR
OUTPUT
GATE
(e.g. 54S05)
DATA
OUT
2
DATA
IN
1
GND 2
Y
0.1
μF
A
GND 1
Y = A
VCC2 = 5 V
STTL
Avago Technologies’ Hi-Rel Optocouplers are in compli-
ance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DLA drawings
5962-89570, and 5962-89571.
Testing consists of 100% screening and quality confor-
mance inspection to MIL-PRF-38534.
Data Rate and Pulse-Width Distortion Definitions
Propagation delay is a figure of merit which describes the
finite amount of time required for a system to translate in-
formation from input to output when shifting logic levels.
Propagation delay from low to high (tPLH) specifies the
amount of time required for a system’s output to change
from a Logic 0 to a Logic 1, when given a stimulus at the
input. Propagation delay from high to low (tPHL) specifies


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