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STM32F100VET6BTR データシート(PDF) 83 Page - STMicroelectronics |
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STM32F100VET6BTR データシート(HTML) 83 Page - STMicroelectronics |
83 / 98 page STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Doc ID 15081 Rev 7 83/98 Note: Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. Figure 33. ADC accuracy characteristics Figure 34. Typical connection diagram using the ADC 1. Refer to Table 51 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 35 or Figure 36, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. EO EG 1LSBIDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VDDA VSSA ai14395b VREF+ 4096 (or depending on package)] VDDA 4096 [1LSBIDEAL = ai14139d STM32F10xxx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter |
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同様の説明 - STM32F100VET6BTR |
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