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ADF4106BRUZ データシート(PDF) 1 Page - Analog Devices |
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ADF4106BRUZ データシート(HTML) 1 Page - Analog Devices |
1 / 24 page PLL Frequency Synthesizer Data Sheet ADF4106 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 6.0 GHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANS Base stations for wireless radios GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. FUNCTIONAL BLOCK DIAGRAM CLK DATA LE REFIN RFINA RFINB 24-BIT INPUT REGISTER SDOUT AVDD DVDD CE AGND DGND 14-BIT R COUNTER R COUNTER LATCH 22 14 FUNCTION LATCH A, B COUNTER LATCH FROM FUNCTION LATCH PRESCALER P/P + 1 N = BP + A LOAD LOAD 13-BIT B COUNTER 6-BIT A COUNTER 6 19 13 M3 M2 M1 MUX SDOUT AVDD HIGH Z MUXOUT CPGND RSET VP CP PHASE FREQUENCY DETECTOR LOCK DETECT REFERENCE CHARGE PUMP CURRENT SETTING 1 ADF4106 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 2 Figure 1. |
同様の部品番号 - ADF4106BRUZ |
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同様の説明 - ADF4106BRUZ |
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