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ADDI7100BCPZ データシート(PDF) 11 Page - Analog Devices |
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ADDI7100BCPZ データシート(HTML) 11 Page - Analog Devices |
11 / 20 page ADDI7100 Rev. C | Page 11 of 20 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ADDI7100 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level that is 1.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always gained appropriately to fill the full-scale range of the ADC. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSBs and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution of the ADC. For example, 1 LSB of the ADDI7100 is 0.5 mV. Power Supply Rejection (PSR) PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the power supply of the ADDI7100. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Internal Delay for SHP/SHD The internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the ADDI7100 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transi- tion from low to high; therefore, the internal delay is measured from the rising edge of each clock to the instant that the actual internal sample is taken. |
同様の部品番号 - ADDI7100BCPZ |
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同様の説明 - ADDI7100BCPZ |
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