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ADuM3220ARZ-RL7 データシート(PDF) 3 Page - Analog Devices

部品番号 ADuM3220ARZ-RL7
部品情報  Isolated, 4 A Dual-Channel Gate Driver
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Data Sheet
ADuM3220/ADuM3221
Rev. C | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 10 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
IDDI(Q)
1.2
1.5
mA
Output Supply Current, Two Channels, Quiescent
IDDO(Q)
4.7
10
mA
Total Supply Current, Two Channels1
DC to 1 MHz
VDD1 Supply Current
IDD1(Q)
1.4
1.7
mA
DC to 1 MHz logic signal frequency
VDD2 Supply Current
IDD2(Q)
11
17
mA
DC to 1 MHz logic signal frequency
Input Currents
IIA, IIB
−10
+0.01
+10
µA
0 V ≤ VIA, VIB ≤ VDD1
Logic High Input Threshold
VIH
0.7 × VDD1
V
Logic Low Input Threshold
VIL
0.3 × VDD1
V
Logic High Output Voltages
VOAH, VOBH
VDD2 − 0.1
VDD2
V
IOx = −20 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.15
V
IOx = +20 mA, VIx = VIxL
Undervoltage Lockout, VDD2 Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
VDD2UV+
4.1
4.4
V
Negative-Going Threshold
VDD2UV−
3.2
3.7
V
Hysteresis
VDD2UVH
0.4
V
ADuM3220B/ADuM3221B
Positive-Going Threshold
VDD2UV+
7.0
7.5
V
Negative-Going Threshold
VDD2UV−
6.0
6.5
V
Hysteresis
VDD2UVH
0.5
V
Output Short-Circuit Pulsed Current2
IOA(SC), IOB(SC)
2.0
4.0
A
VDD2 = 10 V
Output Pulsed Source Resistance
ROA, ROB
0.3
1.3
3.0
VDD2 = 10 V
Output Pulsed Sink Resistance
ROA, ROB
0.3
0.9
3.0
VDD2 = 10 V
SWITCHING SPECIFICATIONS
Pulse Width3
PW
50
ns
CL = 2 nF, VDD2 = 10 V
Data Rate4
1
MHz
CL = 2 nF, VDD2 = 10 V
Propagation Delay5
tDLH, tDHL
35
45
60
ns
CL = 2 nF, VDD2 = 10 V; see Figure 20
tDLH, tDHL
36
50
68
ns
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
Propagation Delay Skew6
tPSK
12
ns
CL = 2 nF, VDD2 = 10 V; see Figure 20
Channel-to-Channel Matching7
tPSKCD
1
5
ns
CL = 2 nF, VDD2 = 10 V; see Figure 20
tPSKCD
1
7
ns
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
Output Rise/Fall Time (10% to 90%)
tR/tF
14
20
25
ns
CL = 2 nF, VDD2 = 10 V; see Figure 20
tR/tF
14
22
28
ns
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
Dynamic Input Supply Current per Channel
IDDI(D)
0.05
mA/Mbps
VDD2 = 10 V
Dynamic Output Supply Current per Channel
IDDO(D)
1.5
mA/Mbps
VDD2 = 10 V
Refresh Rate
fr
1.2
Mbps
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency.
2 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5 t
DLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
6 t
PSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.


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