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SM5545JV-75.0M-T1K データシート(PDF) 6 Page - Pletronics, Inc. |
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SM5545JV-75.0M-T1K データシート(HTML) 6 Page - Pletronics, Inc. |
6 / 8 page SM55J Series 3.3 V CMOS Clock Oscillators March 2013 www.pletronics.com 425-776-1880 6 Mechanical: Inches mm A 0.197 + _0.006 5.00 + _0.15 B 0.126 + _0.006 3.20 + _0.15 C 0.045 + _0.004 1.15 + _0.10 D 0.048 1.23 1 E 0.100 2.54 1 F 0.004 0.10 1 G 0.050 1.27 1 H 0.055 1.40 1 Not to Scale Typical dimensions 1 I 0.024 0.60 1 J 0.004 0.10R 1 K 0.008 0.020R 1 Contacts : Gold 11.8 to 39.4 µinches (0.3 to 1.0 µm) over Nickel 50 to 350 µinches (1.27 to 8.89 µm) Pad Function Note 1 Output Enable/Disable When this pad is not connected the oscillator shall operate. When this pad is logic low the output will be inhibited (high impedance state.) CC Recommend connecting this pad to V if the oscillator is to be always on. 2 Ground (GND) 3 Output 4 Supply Voltage CC (V ) Recommend connecting appropriate power supply bypass capacitors as close as possible. Layout and application information For Optim um Jitter Perform ance, Pletronics recom m ends: • a ground plane under the device • no large transient signals (both current and voltage) should be routed under the device • do not layout near a large m agnetic field such as a high frequency switching power supply • do not place near piezoelectric buzzers or m echanical fans. |
同様の部品番号 - SM5545JV-75.0M-T1K |
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同様の説明 - SM5545JV-75.0M-T1K |
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