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AD7376ARWZ10-RL データシート(PDF) 5 Page - Analog Devices |
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AD7376ARWZ10-RL データシート(HTML) 5 Page - Analog Devices |
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5 / 20 page  AD7376 Rev. D | Page 5 of 20 Parameter Symbol Conditions Min Typ1 Max Unit DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V or 15 V 2.4 V Input Logic Low VIL VDD = 5 V or 15 V 0.8 V Output Logic High VOH RPull-Up = 2.2 kΩ to 5 V 4.9 V Output Logic Low VOL IOL = 1.6 mA, VDD = 15 V 0.4 V Input Current IIL VIN = 0 V or 5 V ±1 µA Input Capacitance6 CIL 5 pF POWER SUPPLIES Power Supply Range VDD/VSS Dual-supply range ±4.5 ±16.5 V Power Supply Range VDD Single-supply range, VSS = 0 4.5 33 V Positive Supply Current IDD VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 2 mA VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V 12 25 µA Negative Supply Current ISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V −0.1 mA VIH = 5 V or VIL = 0 V, VDD/VSS = ±5 V −0.1 mA Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V, VDD/VSS = ±15 V 31.5 mW Power Supply Rejection Ratio PSRR −0.25 ±0.1 +0.25 %/% DYNAMIC CHARACTERISTICS6, 9, 10 Bandwidth −3 dB BW RAB = 50 kΩ, code = 0x40 90 kHz RAB = 100 kΩ, code = 0x40 50 kHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz 0.002 % VW Settling Time tS VA = 10 V, VB = 0 V, ±1 LSB error band 4 µs Resistor Noise Voltage eN_WB RWB = 25 kΩ, f = 1 kHz 2 nV√Hz 1 Typical values represent average readings at 25°C, VDD = 15 V, and VSS = −15 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 Pb-free parts have a 35 ppm/°C temperature coefficient. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. A terminal is open circuit in shutdown mode. 8 PDISS is calculated from (IDD × VDD) + abs(ISS × VSS). CMOS logic level inputs result in minimum power dissipation. 9 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 10 All dynamic characteristics use VDD = 15 V and VSS = −15 V. TIMING SPECIFICATIONS Table 3. Parameter Symbol Conditions Min Typ Max Unit INTERFACE TIMING CHARACTERISTICS1, 2 Clock Frequency fCLK 4 MHz Input Clock Pulse Width tCH, tCL Clock level high or low 120 ns Data Setup Time tDS 30 ns Data Hold Time tDH 20 ns CLK to SDO Propagation Delay3 tPD RPull-Up = 2.2 kΩ, CL < 20 pF 10 100 ns CS Setup Time tCSS 120 ns CS High Pulse Width tCSW 150 ns Reset Pulse Width tRS 120 ns CLK Fall to CS Fall Hold Time tCSH0 10 ns CLK Rise to CS Rise Hold Time tCSH 120 ns CS Rise to Clock Rise Setup tCS1 120 ns 1 Guaranteed by design and not subject to production test. 2 See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 15 V and VSS = −15 V. 3 Propagation delay depends on value of VDD, RPull-Up, and CL. |
同様の部品番号 - AD7376ARWZ10-RL |
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