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AD7841BSZ-REEL データシート(PDF) 5 Page - Analog Devices |
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AD7841BSZ-REEL データシート(HTML) 5 Page - Analog Devices |
5 / 13 page AD7841 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DUTGND_AB Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage applied to this pin. 2, 44, 43, VOUTA ..VOUTH DAC Outputs. 41, 37, 35, 34, 32 3, 4 VREF(–)AB, VREF(+)AB Reference Inputs for DACs A and B. These reference voltages are referred to GND. 5, 38 VDD Positive Analog Power Supply; +15 V ± 10% for specified performance. 6VSS Negative Analog Power Supply; –15 V ± 10% for specified performance. 7 LDAC Load DAC Logic Input (active low). When this logic input is taken low the contents of the registers are transferred to their respective DAC registers. LDAC can be tied permanently low enabling the outputs to be updated on the rising edge of WR. 8, 9, 10 A2, A1, A0 Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a data transfer. 11 CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low. 12 WR Level-Triggered Write Input (active low), used in conjunction with CS to write data to the AD7841 data registers. Data is latched into the selected input register on the rising edge of WR. 13 VCC Logic Power Supply; 5 V ± 5%. 14 GND Ground. 15–28 DB0 . . DB12 Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. 29 CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are switched to the externally set potential on the relevant DUTGND pin. The con- tents of input registers and DAC registers A to H are not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert to their original outputs as determined by the data in their DAC registers. 30, 31 VREF(+)GH, VREF(–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND. 33 DUTGND_GH Device Sense Ground for DACs G and H. VOUTG and VOUTH are referenced to the voltage applied to this pin. 36 DUTGND_EF Device Sense Ground for DACs E and F. VOUTE and VOUTF are referenced to the voltage applied to this pin. 39 VREF(+)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. 40 VREF(–)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND. 42 DUTGND_CD Device Sense Ground for DACs C and D. VOUTC and VOUTD are referenced to the voltage applied to this pin. REV. B |
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