SI5315B-C-GM datasheet(7/54 Pages) SILABS

部品番号	SI5315B-C-GM

部品情報	Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

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Si5315

Rev. 1.0

7

LVCMOS Output Pins

Output Voltage Low

VOL

IO =2mA

VDD =1.62V

——

0.4

V

IO =2mA

VDD =2.97V

——

0.4

V

Output Voltage High

VOH

IO =–2mA

VDD =1.62V

VDD –0.4

—

V

IO =–2mA

VDD =2.97V

VDD –0.4

—

V

Disabled Leakage Current

IOZ

RST = 0

–100

—

100

µA

Single-Ended Reference Clock Input Pin XA (XB with Cap to Gnd)

Input Resistance

XARIN

XTAL/CLOCK = M

—

12

—

k



Input Voltage Level Limits

XAVIN

0—

1.2

V

Input Voltage Swing

XAVPP

0.5

—

1.2

VPP

Differential Reference Clock Input Pins (XA/XB)

Input Resistance

XA/XBRIN

XTAL/CLOCK = M

—

12

—

k



Differential Input Voltage

Level Limits

XA/XBVIN

0—

1.2

V

Input Voltage Swing

XAVPP/XBVPP

0.5

—

2.4

VPP

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Notes:

1. Refers to Si5315A speed grade.

2. Refers to Si5315B speed grade.

3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.

同様の部品番号 - SI5315B-C-GM

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