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SI5330L-A00228-GM データシート(PDF) 8 Page - Silicon Laboratories

部品番号 SI5330L-A00228-GM
部品情報  Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs
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メーカー  SILABS [Silicon Laboratories]
ホームページ  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI5330L-A00228-GM データシート(HTML) 8 Page - Silicon Laboratories

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Si5330
8
Rev. 1.0
Table 9. Absolute Maximum Ratings1,2,3,4,5
Parameter
Symbol
Test Condition
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.8
V
Storage Temperature Range
TSTG
–55 to 150
°C
ESD Tolerance
HBM
(100 pF, 1.5 k
)
2.5
kV
ESD Tolerance
CDM
550
V
ESD Tolerance
MM
175
V
Latch-up Tolerance
JESD78 Compliant
Junction Temperature
TJ
150
°C
Soldering Temperature
(Pb-free profile)5
TPEAK
260
°C
Soldering Temperature Time at TPEAK
(Pb-free profile)5
TP
20–40
sec
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2. 24-QFN package is RoHS compliant.
3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. Moisture sensitivity level is MSL3.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.


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