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TSB81BA3EPFP データシート(PDF) 2 Page - Texas Instruments

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部品番号 TSB81BA3EPFP
部品情報  IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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TSB81BA3E
SLLS783A – MAY 2009 – REVISED MAY 2010
www.ti.com
DESCRIPTION
The TSB81BA3E provides the digital and analog transceiver functions needed to implement a three-port node in
a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB81BA3E is designed to interface
with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4,
TSB42AB4, TSB12LV01B, or TSB12LV01C. It also may be connected cable port to cable port to an integrated
1394 Link + PHY layer such as the TSB43AB2.
The TSB81BA3E can be powered by a single 3.3-V supply when the VREG_PD terminal (terminal 73 on the PFP
package and terminal B7 on the ZAJ package) is tied to GND. VREG_PD enables the internal 3.3-V to 1.95-V
regulator which provides the 1.95-V to the core. The When VREG_PD is pulled high to VDD through at least a
1-k
Ω resistor the TSB81BA3E internal regulator is off and the device can be powered by two separate external
regulated supplies: 3.3-V for the I/Os and 1.95-V for the core. The core voltage is supplied to the PLLVDD-CORE
and DVDD-CORE terminals to the requirements in the recommended operating conditions (1.95-V nominal). The
PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals. The PLLVDD-CORE and the
DVDD-CORE terminals must be decoupled with 1 uF capacitors to stabilze the respective supply. Additional
0.10uF and 0.01uF high-frequency bypass capacitors may also be used. The separation between DVDD-CORE
and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where
the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE
supply.
The TSB81BA3E requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external
clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference
signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz
clock signal is supplied to the associated LLC for synchronization of the two devices and is used for
resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE
1394a-2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the
two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power
down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are received from the LLC on two-, four-, or eight-bit parallel
paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are
latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04
Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information
stream.
The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When
using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link
interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as
the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b
standard.
The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode
of operation is determined by the interface capabilities of the ports being connected. When any of the three ports
is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000
data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b
compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The
TSB81BA3E automatically determines the correct cable interface connection method for the bilingual ports.
NOTE
The BMODE terminal does not select the cable interface mode of operation. The BMODE
terminal selects the PHY-link interface mode of operation and affects the arbitration
modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is
disabled.
During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon
the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system
clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected
and active cable ports.
2
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Product Folder Link(s): TSB81BA3E


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