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AD7801BRZ-REEL データシート(PDF) 7 Page - Analog Devices |
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AD7801BRZ-REEL データシート(HTML) 7 Page - Analog Devices |
7 / 16 page AD7801 –7– REV. 0 TERMINOLOGY Integral Nonlinearity For the DAC, Relative Accuracy or End-Point nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A graphical representation of the transfer curve is shown in Figure 14. Differential Nonlinearity Differential Nonlinearity is the difference between the mea- sured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Zero-Code Error Zero-Code Error is the measured output voltage from VOUT of the DAC when zero code (all zeros) is loaded to the DAC latch. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in LSBs. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale value. It includes full- scale errors but not offset errors. Digital-to-Analog Glitch Impulse Digital-to-Analog Glitch Impulse is the impulse injected into the analog output when the digital inputs change state with the DAC selected and the LDAC used to update the DAC. It is normally specified as the area of the glitch in nV-secs and measured when the digital input code is changed by 1 LSB at the major carry transition. Digital Feedthrough Digital Feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital inputs of the same DAC, but is measured when the DAC is not updated. It is specified in nV-secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. Power Supply Rejection Ratio (PSRR) This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied ±10%. GENERAL DESCRIPTION D/A Section The AD7801 is an 8-bit voltage output digital-to-analog con- verter. The architecture consists of a reference amplifier and a current source DAC followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the DAC. Figure 19 shows a block diagram of the basic DAC architecture. AD7801 VOUT REFIN I/V 11.7k Ω 11.7k Ω CURRENT DAC 30k Ω 30k Ω VDD REFERENCE AMPLIFIER Figure 19. DAC Architecture The DAC output is internally buffered and has rail-to-rail output characteristics. The output amplifier is capable of driving a load of 100 pF and 10 k Ω to both V DD and ground. The reference selection for the DAC can be either internally gener- ated from VDD or externally applied through the REFIN pin. A comparator on the REFIN pin detects whether the required reference is the internally generated reference or the externally applied voltage to the REFIN pin. If REFIN is connected to VDD, the reference selected is the internally generated VDD/2 reference. When an externally applied voltage is more than one volt below VDD, the comparator selection switches to the externally applied voltage on the REFIN pin. The range on the external reference input is from 1.0 V to VDD/2 V. The output voltage from the DAC is given by: VO = 2V REF × N 256 where VREF is the voltage applied to the external REFIN pin or VDD/2 when the internal reference is selected. N is the decimal equivalent of the code loaded to the DAC register and ranges from 0 to 255. VTH PMOS MUX INT REF COMPARATOR SELECTED REFERENCE OUTPUT VDD REFIN INT REF EXT REF Figure 20. Reference Selection Circuitry |
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