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AD9229ABCPZRL7-50 データシート(PDF) 9 Page - Analog Devices |
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AD9229ABCPZRL7-50 データシート(HTML) 9 Page - Analog Devices |
9 / 40 page AD9229 Rev. B | Page 9 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 DRGND DRVDD NC DTP AVDD AGND PDWN AVDD AGND VIN+A VIN–A AGND DRVDD LVDSBIAS AGND AVDD AGND CLK AVDD AGND VIN+D VIN–D AGND 35 DRGND 36 34 33 32 31 30 29 28 27 26 25 AD9229 TOP VIEW (Not to Scale) PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (Bottom of Package) NC = NO CONNECT Figure 3. LFCSP Top View Table 6. Pin Function Descriptions Pin No. Mnemonic Description 5, 8, 16, 21, 29, 32 AVDD Analog Supply 6, 9, 12, 15, 22, 25, 28, 31, 33 AGND Analog Ground 2, 35 DRVDD Digital Output Supply 1, 36 DRGND Digital Ground 0 AGND Exposed Paddle/Thermal Heat Slug (Located on Bottom of Package) 3 NC No Connect 4 DTP Digital Test Pattern Enable 7 PDWN Power-Down Selection (AVDD = Power Down) 10 VIN+A ADC A Analog Input—True 11 VIN–A ADC A Analog Input— Complement 13 VIN–B ADC B Analog Input— Complement 14 VIN+B ADC B Analog Input—True 17 SENSE Reference Mode Selection 18 VREF Voltage Reference Input/Output 19 REFB Differential Reference (Bottom) 20 REFT Differential Reference (Top) 23 VIN+C ADC C Analog Input—True 24 VIN–C ADC C Analog Input— Complement Pin No. Mnemonic Description 26 VIN–D ADC D Analog Input— Complement 27 VIN+D ADC D Analog Input—True 30 CLK Input Clock 34 LVDSBIAS LVDS Output Current Set Resistor Pin 37 D–D ADC D Complement Digital Output 38 D+D ADC D True Digital Output 39 D–C ADC C Complement Digital Output 40 D+C ADC C True Digital Output 41 D–B ADC B Complement Digital Output 42 D+B ADC B True Digital Output 43 D–A ADC A Complement Digital Output 44 D+A ADC A True Digital Output 45 FCO– Frame Clock Indicator— Complement Output 46 FCO+ Frame Clock Indicator—True Output 47 DCO– Data Clock Output— Complement 48 DCO+ Data Clock Output—True |
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