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CDCLVD110AVFRG4 データシート(PDF) 7 Page - Texas Instruments |
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CDCLVD110AVFRG4 データシート(HTML) 7 Page - Texas Instruments |
7 / 18 page CDCLVD110A www.ti.com SCAS841C – FEBRUARY 2007 – REVISED NOVEMBER 2009 APPLICATION INFORMATION Fall-Safe Information For VDD = 0 V (power-down mode) the CDCLVD110A has fail-safe input and output pins. In power-on mode, fail-safe biasing at input pins can be accomplished with a 10-k Ω pullup resistor from CLK0/CLK1 to VDD and a 10-k Ω pulldown resistor from CLK0/CLK1 to GND. LVDS Receiver Input Termination The LVDS receiver inputs require 100- Ω termination resistors placed as close as possible across the input pins. Control Inputs Termination No external termination is required. The CK control input has an internal 120-k Ω pullup resistor, while the SI– and EN–control inputs each have an internal 120-k Ω pulldown resistor. If the control pins are left open per the default, all outputs are enabled, CLK0, CLK0 is selected, and the control register is disabled. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): CDCLVD110A |
同様の部品番号 - CDCLVD110AVFRG4 |
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同様の説明 - CDCLVD110AVFRG4 |
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