SN74AUP1G125DCKR datasheet(9/29 Pages) TI1

部品番号	SN74AUP1G125DCKR

部品情報	LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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VM

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

1 M

Ω

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

tPLH

tPHL

tPLH

VOH

VOL

VI

0 V

Input

Output

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. tPLH and tPHL are the same as tpd.

E. All parameters and waveforms are not applicable to all devices.

VM

5, 10, 15, 30 pF

VCC/2

VCC

VCC = 1.2 V

± 0.1 V

VCC = 0.8 V

VCC = 1.5 V

± 0.1 V

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

VCC = 3.3 V

± 0.3 V

5, 10, 15, 30 pF

VCC/2

VCC

5, 10, 15, 30 pF

VCC/2

VCC

5, 10, 15, 30 pF

VCC/2

VCC

CL

VM

VI

5, 10, 15, 30 pF

VCC/2

VCC

5, 10, 15, 30 pF

VCC/2

VCC

th

tsu

Data Input

Timing Input

VCC

0 V

VCC

0 V

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VCC/2

VCC

VCC/2

SN74AUP1G125

www.ti.com

SCES595L – JULY 2004 – REVISED FEBRUARY 2013

PARAMETER MEASUREMENT INFORMATION

(Propagation Delays, Setup and Hold Times, and Pulse Duration)

Figure 3. Load Circuit and Voltage Waveforms

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Product Folder Links: SN74AUP1G125

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同様の説明 - SN74AUP1G125DCKR

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