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ADP5589ACBZ-02-R7 データシート(PDF) 3 Page - Analog Devices |
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ADP5589ACBZ-02-R7 データシート(HTML) 3 Page - Analog Devices |
3 / 52 page Data Sheet ADP5589 Rev. B | Page 3 of 52 SPECIFICATIONS VDD = 1.8 V to 3.3 V, TA = −40°C to +85⁰C, unless otherwise noted.1 Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY VOLTAGE VDD Input Voltage Range VDD 1.65 3.6 V Undervoltage Lockout Threshold UVLOVDD UVLO active, VDD falling 1.2 1.3 V UVLO inactive, VDD rising 1.4 1.6 V SUPPLY CURRENT Standby Current ISTNBY VDD = 1.65 V 1 4 μA VDD = 3.3 V 1 10 µA Operating Current (One Key Press) ISCAN = 10 ms CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 1.65 V 30 40 µA ISCAN = 10 ms CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 1.65 V 35 45 µA ISCAN = 10 ms CORE_FREQ = 50 kHz, scan active, 300 kΩ pull-up, VDD = 3.3 V 75 85 μA ISCAN = 10 ms CORE_FREQ = 50 kHz, scan active, 100 kΩ pull-up, VDD = 3.3 V 80 90 μA PULL-UP, PULL-DOWN RESISTANCE Pull-Up Option 1 50 100 150 kΩ Pull-Up Option 2 150 300 450 kΩ Pull-Down 150 300 450 kΩ INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10) Logic Low Input Voltage VIL 0.3 × VDD V Logic High Input Voltage VIH 0.7 × VDD V Input Leakage Current (Per Pin) VI-Leak 0.1 1 µA PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4, R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10) Logic Low Output Voltage2 VOL Sink current = 10 mA 0.4 V Logic Low Output Voltage3 VOL Sink current = 10 mA 0.5 V Logic High Output Voltage VOH Source current = 5 mA 0.7 × VDD V Logic High Leakage Current (Per Pin) VOH-Leak 0.1 1 µA OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA) Logic Low Output Voltage (INT) VOL ISINK = 10 mA 0.4 V Logic Low Output Voltage (SDA) VOL ISINK = 20 mA 0.4 V Logic High Leakage Current (Per Pin) VOH-Leak 0.1 1 µA Logic Propagation Delay 125 300 ns FF1 Hold Time4 0 ns FF1 Setup Time4 175 ns FF2 Hold Time4 0 ns FF2 Setup Time4 175 ns GPIO Debounce4 70 µs Internal Oscillator Frequency5 OSCFREQ 900 1000 1100 kHz I2C TIMING SPECIFICATIONS Delay from UVLO/Reset Inactive to I2C Access 60 µs SCL Clock Frequency fSCL 0 1000 kHz SCL High Time tHIGH 0.26 µs SCL Low Time tLOW 0.5 µs Data Setup Time tSU; DAT 50 ns Data Hold Time tHD; DAT 0 µs Setup Time for Repeated Start tSU; STA 0.26 µs |
同様の部品番号 - ADP5589ACBZ-02-R7 |
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同様の説明 - ADP5589ACBZ-02-R7 |
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