TMP275AIDRG4 datasheet(8/19 Pages) TI

部品番号	TMP275AIDRG4

部品情報	0.5 C Digital Out Temperature Sensor

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TMP275

SBOS363D − JUNE 2006 − REVISED AUGUST 2007

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8

A2

A1

A0

SLAVE ADDRESS

0

1001000

0

1

1001001

0

1

0

1001010

0

1

1001011

1

0

1001100

1

0

1

1001101

1

0

1001110

1

1001111

Table 11. Address Pins and Slave Addresses for

the TMP275

BUS OVERVIEW

The device that initiates the transfer is called a master, and

the devices controlled by the master are slaves. The bus

must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates

the START and STOP conditions.

To address a specific device, a START condition is

initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on

the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended.

During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge

and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock

pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as

any change in SDA while SCL is HIGH is interpreted as a

control signal.

Once all data has been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH, while SCL is HIGH.

WRITING/READING TO THE TMP275

Accessing a particular register on the TMP275 is

accomplished by writing the appropriate value to the

Pointer Register. The value for the Pointer Register is the

first byte transferred after the slave address byte with the

R/W bit LOW. Every write operation to the TMP275

requires a value for the Pointer Register. (Refer to

Figure 5.)

When reading from the TMP275, the last value stored in

the Pointer Register by a write operation is used to

determine which register is read by a read operation. To

change the register pointer for a read operation, a new

value must be written to the Pointer Register. This is

accomplished by issuing a slave address byte with the

R/W bit LOW, followed by the Pointer Register Byte. No

additional data is required. The master can then generate

a START condition and send the slave address byte with

the R/W bit HIGH to initiate the read command. See

Figure 6 for details of this sequence. If repeated reads

from the same register are desired, it is not necessary to

continually send the Pointer Register bytes, as the

TMP275 remembers the Pointer Register value until it is

changed by the next write operation.

Note that register bytes are sent most-significant byte first,

followed by the least significant byte.

SLAVE MODE OPERATIONS

The TMP275 can operate as a slave receiver or slave

transmitter.

Slave Receiver Mode:

The first byte transmitted by the master is the slave

address, with the R/W bit LOW. The TMP275 then

acknowledges reception of a valid address. The next byte

transmitted by the master is the Pointer Register. The

TMP275 then acknowledges reception of the Pointer

Register byte. The next byte or bytes are written to the

register addressed by the Pointer Register. The TMP275

acknowledges reception of each data byte. The master

may terminate data transfer by generating a START or

STOP condition.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave

address, with the R/W bit HIGH. The slave acknowledges

reception of a valid slave address. The next byte is

transmitted by the slave and is the most significant byte of

the register indicated by the Pointer Register. The master

acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The

master acknowledges reception of the data byte. The

master may terminate data transfer by generating a

Not-Acknowledge on reception of any data byte, or

generating a START or STOP condition.

SMBus ALERT FUNCTION

The TMP275 supports the SMBus Alert function. When

the TMP275 is operating in Interrupt Mode (TM = 1), the

ALERT pin of the TMP275 may be connected as an

SMBus Alert signal. When a master senses that an ALERT

condition is present on the ALERT line, the master sends

an SMBus Alert command (00011001) on the bus. If the

ALERT pin of the TMP275 is active, the device

acknowledges the SMBus Alert command and responds

by returning its slave address on the SDA line. The eighth

bit (LSB) of the slave address byte indicates if the

temperature exceeding THIGH or falling below TLOW

caused the ALERT condition. This bit will be HIGH if the

temperature is greater than or equal to THIGH. This bit will

be LOW if the temperature is less than TLOW. Refer to

Figure 7 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert

command, arbitration during the slave address portion of

the SMBus Alert command determines which device will

clear its ALERT status. If the TMP275 wins the arbitration,

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