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HCPL-0738 データシート(PDF) 7 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-0738 データシート(HTML) 7 Page - AVAGO TECHNOLOGIES LIMITED |
7 / 8 page 7 Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagationdelayisafigureofmeritwhichdescribeshow quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the in- put signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maxi- mum data rate capability of a transmission system. PWD Figure 6. Recommended printed circuit board layout. Application Information Bypassing and PC Board Layout The HCPL-0738 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL- 0738useshigh-speedCMOSICtechnologyallowingCMOS logic to be connected directly to the inputs and outputs. can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to con-sider in parallel data applications where synchro- nization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of op- tocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. AsshowninFigure6,theonlyexternalcomponentrequired forproperoperationisthebypasscapacitor.Capacitorvalues should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. 7 5 6 8 2 3 4 1 GND 2 C VDD GND 1 VO 2 VO 1 IF1 GND 1 IF2 |
同様の部品番号 - HCPL-0738 |
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同様の説明 - HCPL-0738 |
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